1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device.
2. Description of the Related Art
A nonvolatile semiconductor memory device can hold information without a power supply, and hence is widely used in various devices such as a portable information device. In many information devices, permanent information which is stored at factory shipment (for the sake of convenience, hereinafter referred to as “fixed information”) is stored in a memory such as a mask ROM (Read Only Memory), and information which is to be written and rewritten in a stage where the user uses the information (for the sake of convenience, hereinafter referred to as “semi-fixed information”) is stored in an EEPROM (Electrically Erasable Programmable ROM) or the like.
Usually, an EEPROM comprises a charge storage layer between a gate electrode and a semiconductor substrate to store charges, thereby storing semi-fixed information. This storing process uses a phenomenon that, when charges in the charge storage layer are negative, the amount of ON-current is decreased, and, when the charges are positive, the amount of ON-current is increased. As a charge storage layer, useful is a floating gate formed by a conductor surrounded by an insulating layer, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) layer structure formed by a stack of insulating layers and conductive layers, an MNOS (Metal-Nitride-Oxide-Semiconductor) layer structure, or the like.
Conventionally, fixed information and semi-fixed information cannot be stored in the same element. Therefore, a mask ROM region and an EEPROM region are separately mounted in an information device. As a result, there arise problems in that a nonvolatile semiconductor memory device occupies a larger area, and that such a device has a complicated configuration.
Therefore, a configuration in which fixed information and semi-fixed information are stored in the same storage element has been proposed (see Japanese Patent No. 3,420,165). The storage of fixed information is carried out depending on whether a source impurity diffusion layer exists or not in a storage element, based on a phenomenon that the amount of ON-current is small in an EEPROM having no source impurity diffusion layer. Semi-fixed information is stored depending on the amount of charges in a charge storage layer in the same manner as a usual EEPROM.
The operation of reading semi-fixed information is conducted by reversing the source and the drain. When the roles of source and drain are reversed, previously stored fixed information is changed so as to depend on the presence/absence of a drain impurity diffusion layer. As compared with the presence/absence of a source impurity diffusion layer and the positive/negative of charges in a charge storage layer, the presence/absence of a drain impurity diffusion layer less affects the amount of ON-current. Therefore, the ON-current is most affected by the positive/negative of charges in a charge storage layer, and can reflect the semi-fixed information with high ON/OFF characteristics.
However, the reversion of source and drain means that a further restriction must be imposed on the circuit design, and often causes the circuit to be complicated.
On the other hand, a storage element has been proposed in which a charge storage layer is formed on side faces of a gate electrode on both the source and drain sides, and charges are stored in each of the charge storage layers to store 2-bit semi-fixed information. However, the proposed storage element has a problem in that charges in the charge storage layers on the source and drain sides mutually affect each other and hence has low ON/OFF characteristics.
Therefore, a method of improving ON/OFF characteristics in a configuration where charge storage layers are formed by a stack structure such as MONOS or MNOS has been proposed (see JP-A-2003-203998). In the proposed method, in writing and reading operations, a voltage is applied to the gate electrode in the course of voltage application between the source/drain regions. However, this method requires means for controlling the timing of the voltage application, and hence has a problem in that the structure of a storage element is complicated and enlarged.